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NCP5210 Product Preview 3-In-1 PWM Dual Buck and Linear DDR Power Controller
The NCP5210, 3-In-1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage. This IC contains two synchronous PWM buck controller for driving four external NFETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of the reference voltage with sourcing and sinking current. Protective features include, soft-start circuitry, under-voltage monitoring of 5VDUAL, and BOOT voltage, and thermal shutdown. The IC is packaged in QFN-20.
Features http://onsemi.com MARKING DIAGRAMS
NCP5210 AWLYYWW 1 18
1 20-LEAD QFN MN SUFFIX CASE 505
* Incorporates Synchronous PWM Buck Controllers for VDDQ and * * * * * * * * * * * * *
VMCH Integrated Power FETs with VTT Regulator Source/Sink up to 1.8 A All External Power MOSFETs are N-channel Adjustable VDDQ and VMCH by External Dividers VTT Tracks at Half the Reference Voltage Fixed Switching Frequency of 250 kHz for VDDQ and VMCH Doubled Switching Frequency (500 kHz) for VDDQ Controller in Standby Mode to Optimize Inductor Current Ripple and Efficiency Soft-start Protection for all Controllers Under-V oltage Monitor of Supply Voltages Over-Current Protections for DDQ and VTT Regulators Fully Complies with ACPI Power Sequencing Specifications Short Circuit Protection Prevents Damage to Power Supply Due to Reverse DIMM Insertion Thermal Shutdown 20-Lead 5x6 QFN Package
NCP5210 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
PIN CONNECTIONS
COMP FBDDQ SS PGND VTT VDDQ AGND FBVTT DDQ_REF FB1P5 SW_DDQ BG_DDQ TG_TDQ BOOT 5VDUAL COMP_1P5 BUF_Cut TG_1P5 BG_1P5 GND_1P5
Typical Applications
* DDR I and DDR II Memory and MCH Power Supply
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
ORDERING INFORMATION
Device NCP5210MN Package 20-Lead QFN* Shipping Rail Tape and Reel
NCP5210MNR2 20-Lead QFN* *5 x 6 mm
(c) Semiconductor Components Industries, LLC, 2003
1
September, 2003 - Rev. P0
Publication Order Number: NCP5210/D
NCP5210
BUF_Cut BUF_Cut SS 12 V CSS BOOT 1.25 V, 1.8 Apk COUT2 FBVTT VTT VTT 5VDUAL 13 V Zener 5VDUAL
AGND DDQ_REF VDDQ CZM2 R5 RZM2 CZM1 CPM1 RZM1 5VDUAL R6 M3 VMCH L FBDDQ TG_1P5 COMP_1P5 BGDDQ FB_1P5 PGND COMP CZ1 RZ1 TGDDQ
M1 L VDDQ 2.5 V, 20 A COUT1 M2
NCP5210
SWDDQ
CZ2 R1
CP1
RZ2
R2 1.5 V, 10 A COUT3 M4 BG_1P5 VDDQ PGND
Figure 1. Application Diagram
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VREF VOLTAGE and CURRENT REFERENCE BUF_CUT VCC BOOT_ R10 R11 VREF 5VDUAL R12 R13 _5VDLGD VREF VDDQ and V1P5 PWM LOGIC PGND VCC 5VDUAL_ UVLO INREGMCH INREGDDQ ILIM + IREF VCC - UVLO _BOOTGD CONTROL LOGIC S0 S3
VCC THERMAL SHUTDOWN
12 V BOOT
_VREFGD TSD
13 V Zener
5VDUAL 5VDUAL
RL1
5VDUAL
M1 TG_DDQ SW_DDQ L VDDQ
COUT1 BG_DDQ PGND M2
PGND CSS OSC S0 S3 AMP A1 VCC 1805 Phase Shift VREF COMP CZ1 RZ1 FBDDQ CZ2 CP1 RZ2 5VDUAL M3 TP_1P5 PGND BG_1P5 GND_1P5 PGND AMP_MCH VREF A1 CZM1 RZM1 FBDDQ COMP_1P5 CZM2 CPM1 RZM2 RM2 M4 L2 R2 VMCH
R1
COUT2
RM1
DDQ_REF 5VDUAL S0 R16 VTT Regulation Control R17 R18 R19 AGND 5VDUAL M3 M2 VTT VTT COUT2 VDDQ
AGND
AGND
PGND
FBVTT
Figure 2. Internal Block Diagram
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PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol COMP FBDDQ SS PGND VTT VDDQ AGND FBVTT DDQ_REF FB1P5 GND_1P5 BG_1P5 TG_1P5 BUF_Cut COM_1P5 5VDUAL BOOT TG_DDQ BG_DDQ SW_DDQ VDDQ error amplifier compensation node DDQ regulator feedback pin for closed loop regulation Soft-start pin of DDQ regulator connecting a capacitor Power ground VTT regulator output Power input for VTT linear regulator Analog ground connection and remote ground sense VTT regulator feedback pin for closed loop regulation Reference voltage input of VTT regulator V1P5 Switching Regulator feedback pin for closed loop regulation Power ground for V1P5 regulator Gate driver output for V1P5 regulator low side N-Channel Power FET Gate driver output for V1P5 regulator high side N-Channel Power FET Active High control signal to activate S3 Sleep State V1P5 error amplifier compensation node 5V Dual supply input, which is monitored by under-voltage lock out circuitry Gate driver input supply, which is monitored by under-voltage lock out circuitry, and a boost capacitor connection between SWDDQ and this pin Gate driver output for DDQ regulator high side N-Channel Power FET Gate driver output for DDQ regulator low side N-Channel Power FET DDQ regulator inductor driven node and current limit sense input Description
MAXIMUM RATINGS
Rating Power Supply Voltage (Pin 16) to AGND (Pin 7) Gate Drive Voltage (Pin 12, 13, 17-19) to AGND (PIN 7) Input / Output Pins to AGND (Pin 7) Pin 1-6, 8-11, 14-16, 20 Thermal Characteristics QFN-20 Plastic Package Thermal Resistance Junction to Air Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol 5VDUAL VCC, Vg VIO RqJA Value -0.3, 6.0 -0.3, 14 -0.3, 6.0 35(TBD) Unit V V V C/W
TJ TA Tstg MSL
0 to + 150 0 to + 70 - 55 to +150 2
C C C
1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115. 2. Latch-up Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0C to 70C, L = 1.7 mH,
COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF, RL1 = 200 kW, R1 = 2.166 kW, R2 = 2 kW, RZ1 = 20 kW, RZ2 = 8 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2 kW, RZM1 = 20 kW, RZM2 = 8 W, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nf for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ. Characteristic SUPPLY VOLTAGE 5VDUAL Operating Voltage BOOT Operating Voltage SUPPLY CURRENT S0 mode Supply Current from 5VDUAL S3 mode Supply Current from 5VDUAL S5 mode Supply Current from 5VDUAL S0 mode Supply Current from BOOT BUF_Cut = LOW, BOOT = 12 V BUF_Cut = HIGH BUF_Cut = LOW, BUF_Cut = LOW, BOOT = 12 V, TGDDQ, BGDDQ , TG_1P5 and BG_1P5 Open BUF_Cut=HIGH, TGDDQ, BGDDQ, TG_1P5 and BG_1P5 Open I5VDL_S0 I5VDL_S3 I5VDL_S5 IBOOT_S0 1 20 6 mA mA mA mA V5VDUAL VBOOT 4.5 8.0 5.0 12.0 5.5 13.2 V V Test Conditions Symbol Min Typ Max
Unit
S3 mode Supply Current from BOOT UNDER-VOLTAGE-MONITOR 5VDUAL UVLO Upper Threshold 5VDUAL UVLO Hysteresis BOOT UVLO Upper Threshold BOOT UVLO Hysteresis THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis DDQ SWITCHING REGULATOR FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency in S0 Mode Oscillator Frequency in S3 Mode Current Limit Blanking Time in S0 Mode Minimum Duty Cycle Maximum Duty Cycle Soft-Start Pin Current for DDQ DDQ ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate VTT ACTIVE TERMINATION REGULATOR VTT tracking DDQ_REF/2 at S0 mode
IBOOT_S3
20
mA
V5VDLUV+ V5VDLhys VBOOTUV+ VBOOThys 1 300
4.4
V mV
10.2
V V
Tsd Tsdhys
150 25
C C
Ta = 25C Ta = 0C to 70C V(FBDDQ) = 1.3 V
VFBQ IDDQfb FDDQS0 FDDQS3 TDDQbk Dmin Dmax
1.188 1.176
1.200
1.212 1.224 1
V mA KHz KHz nS %
225 450 400 0
250 500
275 550
100 4
% mA
V(SS) = 0.5 V
Iss1
GAINDDQ COMP PIN to GND = 220nF, 1 W in Series COMP PIN TO GND = 10 pF GBWDDQ SRDDQ
70 TBD 8
dB MHz V/uS
IOUT= 0 to 1.8A (sink current)IOUT= 0 to -1.8A (source current)
dVTTS0
-30
30
mV
VTT Source Current Limit VTT Sink Current Limit DDQ_REF Input Resistance
ILIMVTsrc ILIMVTsnk DDQREF
2.4 2.4 50
A A W
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ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0C to 70C, L = 1.7 mH,
COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF, RL1 = 200 kW, R1 = 2.166 kW, R2 = 2 kW, RZ1 = 20 kW, RZ2 = 8 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2 kW, RZM1 = 20 kW, RZM2 = 8 W, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nf for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ. Characteristic CONTROL SECTION BUF_Cut Input Logic HIGH BUF_Cut Input Logic LOW BUF_Cut Input Current GATE DRIVERS TGDDQ Gate pull-HIGH Resistance TGDDQ Gate pull-LOW Resistance BGDDQ Gate pull-HIGH Resistance BGDDQ Gate pull-LOW Resistance TG1P5 Gate pull-HIGH Resistance TG1P5 Gate pull-LOW Resistance BG1P5 Gate pull-HIGH Resistance BG1P5 Gate pull-LOW Resistance MCH SWITCHING REGULATOR VFB1P5 Feedback Voltage, control loop in regulation Feedback Input Current Oscillator Frequency Minimum Duty Cycle Maximum Duty Cycle Soft-start Pin Current for V1P5 regulator Ta = 0C to 70C VFB1P5 I1P5FB F1P5 Dmin_1P5 Dmax_1P5 ISS2 8 225 0 100 250 0.784 0.8 0.816 1 275 V mA KHz % % mA VCC = 12 V, V(TGDDQ) = 11 V VCC = 12 V, V(TGDDQ) = 1 V VCC = 12 V, V(BGDDQ) = 11 V VCC = 12 V, V(BGDDQ) = 1 V VCC = 12 V, V(TG1P5) = 11 V VCC = 12 V, V(TG1P5) = 1 V VCC = 12 V, V(BG1P5) = 11 V VCC = 12 V, V(BG1P5) = 1 V RH_TG RL_TG RH_BG RL_BG RH_TPG RL_TPG RH_BPG RL_BPG 3 2.5 3 1.3 3 2.5 3 1.3 W W W W W W W W Logic_H Logic_L Ilogic 2.0 0.8 1 V V mA Test Conditions Symbol Min Typ Max
Unit
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DETAILED OPERATION DESCRIPTIONS
General
The NCP5210 3-In-1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two-quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external NFETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at 1/2 VDDQ. The MCH core voltage is created by the secondary switching controller. The inclusion of soft-start, supply under-voltage monitors, short circuit protection and thermal shutdown, makes this device a total power solution for the MCH and DDR memory system. This device is packaged in a QFN-20.
ACPI Control Logic
The ACPI control logic is enabled by the assertion of _VREFGD. Once the ACPI control is activated, the power up sequence starts by waking up the 5VDUAL voltage monitor block. If the 5VDUAL supply is within the preset levels, the BOOT under voltage monitor block is then enabled. After the BOOT UVLO is asserted HIGH, the ACPI control triggers this device from S5 shutdown mode into S0 normal operating mode by activating the soft-start of DDQ switching regulator, providing BUF_CUT remaining LOW. Once the DDQ regulator is in regulation and the soft-start interval is completed, the _InRegDDQ signal is asserted HIGH to enable the VTT regulator as well as the V1P5 switching regulator.
DDQ Switching Regulator
The ACPI control logic is powered by the 5VDUAL supply. It accepts external control at the BUF_CUT input, and internal supply voltage monitoring signals from two UVLOs to decode the operating mode in accordance with state transition diagram in Figure 3. These UVLOs monitor the external supplies, 5VDUAL and 12VATX, through 5VDUAL and BOOT pins respectively. Two control signals, _5VDUALGD and _BOOTGD, are asserted when the supply voltages are good. The device powers up initially in the S5 shutdown mode to minimize the power consumption. When all three supply voltages are good and BUF_CUT is LOW, the device enters the S0 normal operating mode. When BUF_CUT transitions from LOW to HIGH in S0 mode the device goes into the S3 sleep mode. In S3 mode the 12VATX supply collapses. On transition of BUF_CUT from HIGH to LOW, the device returns to S0 mode. The IC re-enters S5 mode if one of the supplies is removed during S0 mode. Transitions from S3 to S5 or vice versa are not allowed. A timing diagram is shown in Figure 3. Table 1 summarizes the operating states of all the regulators, as well as the conditions of output pins.
S5 To S0 Mode Power Up Sequence
In S0 mode the DDQ regulator is a switching synchronous rectification buck controller driving two external power NFETs to supply up to 20 A. It employs voltage mode fixed frequency PWM control with external compensation switching at 250kHz 10%. As shown in Figure 2, the VDDQ output voltage is divided down and fed back to the inverting input of an internal amplifier through the FBDDQ pin to close the loop at VDDQ = VFBQ x (1 + R2/R1). This amplifier compares the feedback voltage with an internal reference voltage of 1.200 V to generate an error signal for the PWM comparator. This error signal is compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. The PWM signal drives the external NFETs via the TG_DDQ and BG_DDQ pins. External inductor L and capacitor COUT1 filter the output waveform. When the IC leaves the S5 state, the VDDQ output voltage ramps up at a soft-start rate controlled by the capacitor at the SS pin. When the regulation of VDDQ is detected in S0 mode, _INREGDDQ goes HIGH to notify the control block. In S3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external NFETs.
An internal bandgap reference is generated whenever 5VDUAL exceeds 2.7 V. Once this bandgap reference is in regulation, an internal signal _VREFGD is asserted.
Table 1. Mode, Operation and Output Pin Condition
OPERATING CONDITIONS MODE S0 S3 S5 DDQ Normal Standby H-Z VTT Normal H-Z H-Z TGDDQ Normal Standby Low OUTPUT PIN CONDITIONS BGDDQ Normal Standby Low TP_1P5 Normal Low Low BG_1P5 Normal Low Low
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For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non-overlap timing control of the complementary gate drive output signals is provided to reduce shoot-through current that degrades efficiency.
Tolerance of VDDQ
at the half of DDQ_REF. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 1-mW to 400 mW.
Fault Protection of VTT Active Terminator
Both the tolerance of VFBQ and the ratio of the external resistor divider R2/R1 impact the precision of VDDQ. With the control loop in regulation, VDDQ = VFBQ x (1 + R2/R1). With a worst case (for all valid operating conditions) VFBQ tolerance of 1.5%, a worst case range of 2% for VDDQ will be assured if the ratio R2/R1 is specified as 0.9455 1%.
Fault Protection of VDDQ Regulator
To provide protection for the internal FETs, bi-directional current limit preset at 2.4 A magnitude is implemented. This current limit is also used as constant current source during VTT startup.
MCH Switching Regulator
The secondary switching regulator is identical to the DDQ regulator except the output is 10 A, no fault protection is implemented and the soft-start timing is twice as fast with respect to CSS.
BOOT Pin Supply Voltage
In S0 mode, an internal voltage (VOCP) = 5VDUAL - 0.8 sets the current limit for the high-side switch. The voltage VOCP pin is compared to the voltage at SWDDQ pin when the high-side gate drive is turned on after a fixed period of blanking time to avoid false current limit triggering. When the voltage at SWDDQ is lower than VOCP, an over-current condition occurs and all regulators are latched off to protect against over-current. The IC can be powered up again if one of the supply voltages, 5VDUAL or 12VATX, is recycled. In S3 mode, this over-current protection feature is disabled.
Feedback Compensation of VDDQ Regulator
In typical application, a flying capacitor is connected between SWDDQ and BOOT pins. In S0 mode, 12VATX is tied to BOOT pin through a Schottky diode as well. A 13-V Zener clamp circuit must clamp this boot strapping voltage produced by the flying capacitor in S0 mode. In S3 mode the 12VATX is collapsed and the BOOT voltage is created by the Schottky diode between 5VDUAL and BOOT pins as well as the flying capacitor.
Thermal Consideration
The compensation network is shown in Figure 2.
VTT Active Terminator
The VTT active terminator is a 2 quadrant linear regulator with two internal NFETs to provide current sink and source capability up to 1.8A. It is activated only when the DDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT pin directly, VTT voltage is designed to automatically track
Assuming an ambient temperature of 50C, the maximum allowed dissipated power of QFN-20 is 2.8 W, which is enough to handle the internal power dissipation in S0 mode. To take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact.
Thermal Shutdown
When the junction temperature of the IC exceeds 150C, the entire IC is shutdown. When the junction temperature drops below 115C, the chip resumes normal operation.
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5VSTBY or 5VDUAL 12 V 5V BUF_CUT SS pin DDQ-S0 Switching Frequency Doubles
VTT MCH
State
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15 16
17
SO
S3
SO
S5
Figure 3. NCP5210 Power-up and Power-down
2. 5VSTBY or 5VSTB is the Ultimate Chip Enable. This supply has to be up first to ensure gates are in known state. 3. 12 V and 5 V supplies can ramp in either order. 4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * CSS / 4 m (sec). 5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground. 5. MCH ramps with the tracking of SS pin ramp, timing is 1.2 * CSS / 8 m (sec). VTT rises. 6. MCH SS is completed, then SS pin is released from MCH. SS pin is shorted to ground. S0 Mode. 7. S3 MODE - BUF_CUT = H 8. VTT and MCH will be turned off. 9. 12 V and 5 V ramps to 0 V. 10. Standard S3 State 11. 12 V and 5 V ramps back to regulation. 12. BUF_CUT goes LOW 13. 12 V UVLO = L and BUF_CUT = L. MCH ramps with SS pin, timing is 1.2 * CSS / 8 m (sec). VTT rises. 14. S0 Mode 15. S5 Mode - BUF_CUT = L, and 12VUVLO = H or 5VUVLO = H 16. DDQ, VTT, and MCH Turned OFF 17. S5 Mode
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S5
BUF_CUT = 0 AND _BOOTGD = 1 AND
BUF_CUT = 0 AND (_BOOTGD = 0)
S0
BUF_CUT = 0 AND _BOOTGD = 1 AND
BUF_CUT = 1
NOTE: All possible state transitions are shown. All unspecified inputs do not cause any state change.
S3
Figure 4. Transitions State Diagram of NCP5210
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PACKAGE DIMENSIONS
QFN MN SUFFIX CASE 505-01 ISSUE A
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.23 0.28 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.50 0.60
PIN 1 LOCATION
E 0.15 C 0.15 C
0.10 C A2 0.08 C A1 A3
REF
A C
SEATING PLANE
DIM A A1 A2 A3 b D D2 E E2 e K L
D2
18 X
L
e
1 9
18 X
K
18 10 18 X b
E2
0.10 C A B 0.05 C
NOTE 3
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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP5210/D

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